The invention relates to a semiconductor device of the type having a semiconductor body comprising a substrate region of a first conductivity type, a semiconductor layer of the second opposite conductivity type disposed thereon and forming a pn junction with the substrate region, and a bipolar transistor having a surface-adjoining base zone of the first conductivity type, an emitter zone of the second conductivity type provided in the base zone, a highly doped buried layer of the second conductivity type present between the substrate region and the semiconductor layer and located below the base zone, a surface-adjoining collector contact zone of the second conductivity type and a gate electrode disposed between the base zone and the collector contact zone and separated by a barrier layer from the semiconductor layer.
Such a semiconductor device is described in European Patent Specification EP No. 45447.
For transistors used in circuits in which high voltages are utilized, often a construction is chosen consisting of a vertical bipolar transistor formed in a semiconductor layer and a lateral junction field effect transistor, one gate electrode of which is constituted by the substrate. The substrate is then of a conductivity type opposite to that of the semiconductor layer.
Two embodiments of this structure are described in European Patent Specification EP No. 45447.
In the first embodiment, the base zone of a vertical pnp transistor extends in projection beyond the buried layer and thus constitutes a further gate electrode of the field effect transistor, whose channel is constituted by a part of the collector region (the semiconductor layer).
If the transistor is operated so that the collector has a high voltage with respect to the emitter, the base and the substrate, the field effect transistor is depleted both from the side of the surface and from the side of the substrate. Depletion throughout the thickness of the semIconductor layer between the base zone and the substrate occurs at a voltage below the breakdown voltage (the so-called RESURF principle), as a result of which very high collector-base voltages can be used, while under the influence of the comparatively strong electric field parallel to the surface substantial emitter-collector currents can nevertheless flow.
In emitter-follower operation, the emitter, the base and the collector all have a high voltage with respect to the substrate. The semiconductor layer in this case is depleted only from the substrate, while a part of the thickness of the semiconductor layer remains undepleted so that even with a low emitter-collector voltage a sufficiently high current can flow through the semiconductor layer. A serious limitation for operation in the emitter follower configuration is the fact, however, that the outer part of the base zone may form, with the semiconductor layer and the substrate a bipolar parasitic pnp transistor. When in the case of overdrive of the npn transistor the base-collector junction is biased in the forward direction, a large hole current is injected via this pnp transistor, which is very undesirable and may lead to irreparable damage of the device. This embodiment is therefore less suitable for operation in emitter follower configuration.
According to a second embodiment described in the aforementioned European Patent Specification EP No. 45447, the buried layer extends below the entire base zone of the npn transistor and a further gate electrode of the field effect transistor is constituted by a separate P-type surface zone, which is electrically connected to the substrate. This embodiment is less suitable either for operation in emitter follower configuration. At the high voltage then prevailing at the emitter, the base and the collector with respect to the substrate, the semiconductor layer is entirely depleted from both gate electrodes (substrates and p-type surface zone). At a low emitter-collector voltage, in the absence of a sufficiently strong electric field parallel to the surface, no current can flow through the depleted part of the semiconductor layer so that the device cannot operate, appropriately.